MATHS implements a 1-bit set-reset flip-flop with CH1 Trigger as Set and BOTH CV as Reset

MATHS Channel 1 can implement a set-reset flip-flop (1-bit memory): the Trigger Input acts as ‘Set’ and the BOTH Control Input acts as ‘Reset.’ Patch: Rise full CCW, Fall full CW, Vari-Response Linear; the gate/logic signal to CH1 Trigger sets it, the reset pulse to CH1 BOTH CV clears it. Take the ‘Q’ output from EOC, and patch EOC to CH4 Signal to derive ‘NOT Q.’ Because the state is held as an analog charge rather than a true digital latch, it leaks: the patch has a memory limit of about three minutes, after which it forgets its stored bit. It demonstrates that MATHS can realise digital logic primitives from analog circuitry, useful for state-holding behaviours within a patch.

Examples

A sequence repeatedly triggers CH1 (Set); a button sends a reset pulse to BOTH CV (Reset), clearing the latch; Q is read from EOC.

Assessment

Which input acts as Set and which as Reset in the MATHS flip-flop, and where do you read Q? Why does the stored bit decay after roughly three minutes?