Maths generates a voltage-controlled clock by taking EOC or EOR from a self-cycling channel

By setting Maths CH.1 or CH.4 to self-cycle and taking output from EOC or EOR, the module generates a pulse clock. On CH.1, RISE primarily controls frequency and FALL adjusts pulse width. On CH.4 the roles swap. The CYCLE IN jack acts as a voltage-controlled Run/Stop gate. This is the basis for all clock-source and rhythmic trigger applications of Maths.

Examples

CH.1 to self-cycle (CYCLE switch on). Take output from EOR. Patch a control voltage to CYCLE IN to start/stop. Patch SUM OUT to BOTH IN for voltage-controlled rate.

Assessment

On CH.1, which parameter primarily sets clock frequency and which sets pulse width? What are the roles reversed to on CH.4?